//~ `New testbench
`timescale  1ns / 1ps

module tb_keyexp;

// keyexp Parameters
parameter PERIOD  = 10;


// keyexp Inputs
reg   clk                                  = 1 ;
reg   rst_n                                = 0 ;
reg   keysel                               = 0 ;
reg   rd_en_keyexp_regs                    = 0 ;
reg   wr_en_keyexp_regs                    = 0 ;
reg   [3:0]  addr                          = 0 ;
reg   rcon_en                              = 0 ;
reg   [127:0]  key                         = 0 ;

// keyexp Outputs
wire  [127:0]  exp_key                     ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst_n  =  1;
end

keyexp  u_keyexp (
    .clk                     ( clk                        ),
    .rst_n                   ( rst_n                      ),
    .keysel                  ( keysel                     ),
    .rd_en_keyexp_regs       ( rd_en_keyexp_regs          ),
    .wr_en_keyexp_regs       ( wr_en_keyexp_regs          ),
    .addr                    ( addr               [3:0]   ),
    .rcon_en                 ( rcon_en                    ),
    .key                     ( key                [127:0] ),

    .exp_key                 ( exp_key            [127:0] )
);
integer i;

initial
begin
    #(PERIOD*2+7);
    key = 128'h2b7e151628aed2a6abf7158809cf4f3c;
    key = 128'h00112233445566778899aabbccddeeff;
    keysel = 0; 
    wr_en_keyexp_regs=1;
    addr = 'd0;
    rcon_en = 0;
    rd_en_keyexp_regs=1;

    #(PERIOD);
    keysel = 1;
    rcon_en = 1;
    for(i=1;i<10;i=i+1)begin
        addr = addr + 1'b1;
        #(PERIOD);
    end
    
    wr_en_keyexp_regs = 0;
    rd_en_keyexp_regs = 0;
    rcon_en = 0;

    #(PERIOD*100);
    addr =0;
    #(PERIOD);
    for(i=0;i<10;i=i+1)begin
        addr = addr + 1;
        #(PERIOD);
    end

    $stop;
end

endmodule